1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a capacitorless dynamic random access memory (DRAM) and a fabrication method thereof.
2. Description of the Related Art
A typical DRAM is configured with one transistor and one capacitor. This structural configuration is denoted as “1T/1C” hereinafter. However, when 1T/1C DRAMs are embedded into a chip with other devices, formation of capacitors gets complicated due to the large integration scale of chips.
Hence, other types of DRAM, which can store data without a capacitor, have been suggested. One example of such a DRAM is a capacitorless DRAM that stores charges into a body of a substrate.
FIGS. 1A and 1B are cross-sectional views illustrating operation of a capacitorless DRAM. Referring to FIG. 1A, a high voltage is applied to a gate 20 and a drain 11 to generate excess holes 1, which are hot carriers, in a channel body 13 of a substrate. Since an oxide barrier 10 is formed beneath the channel body 13, the excess holes 1 cannot escape. As a result, the excess holes 1 are kept within the channel body 13. This confinement state of the excess holes 1 within the channel body 13 is stored as “1.” Referring to FIG. 1B, current flows between a source 12 and the drain 11 to remove the excess holes 1 from the channel body 13. This escape state of the excess holes 1 from the channel body 13 is stored as “0.” When a corresponding transistor is selected, depending on a storage state, i.e., “1” or “0,” a threshold voltage level is different and a current level also varies. Using this variation, a read operation is executed.
The excess holes within the channel body generally disappear via recombination as time elapses. A time till the excess holes disappear is called retention time. Thus, a method of elongating the retention time is an important consideration for improving efficiency of a capacitorless 1T DRAM.